GenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration

Last update: Dec 15, 2022

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Overview

GenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration

Stefan Abi-Karam*, Yuqi He*, Rishov Sarkar*, Lakshmi Sathidevi, Zihang Qiao, Cong Hao (*equal contribution; ordered alphabetically)

School of Electrical and Computer Engineering, Georgia Institute of Technology

Overview

This is GenGNN, a generic GNN acceleration framework using High-Level Synthesis (HLS) with two-fold goals. First, we aim to deliver ultra-fast GNN inference without any graph pre-processing for real-time requirements. Second, we aim to support a diverse set of GNN models with the extensibility to flexibly adapt to new models.

Currently, this repository contains prebuilt bitstreams for the Xilinx Alveo U50 FPGA along with supporting host code. Our HLS code will be open-source upon acceptance.

Owner

Sharc-Lab

Software/hardware Co-design Lab at Georgia Tech

GitHub Repository

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GenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration

Related tags

Overview

GenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration

Overview

Owner

Sharc-Lab

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