Got this message from JLCPCB and they cancelled my order:

"After marking the hole compensation of the original 0.4/0.6 mm, the minimum hole distance is only about 0.17 mm, and the minimum hole distance line is only about 0.08, which exceeds our capabilities. (the minimum hole distance of different networks must be greater than 0.33 mm , the hole distance line must be greater than 0.23 mm)"

I did notice that the visa and tracks were awfully close to each other, but i figured you had submitted this to JLCPCB before so i didn’t think it was an issue.

I’d do this myself, but modifying this design to fix this issue messes with it far more than I am comfortable with.

the full list of capabilities can be found here: https://jlcpcb.com/capabilities/Capabilities

Thanks for posting this repo! I had some success with it on the TinyFPGA-Bx using the DirectUSB resource.

This target enumerates correctly and the dummy tone shows up on record (a tad off-key and with a few artefacts)

I added back the custom rules and changed them so that:

1. the custom rules that duplicated global rules were commented out
2. the minimum clearance rule for the inner layers has been changed so it doesn't apply to zones, so it won't have the same copper fill bug that it did before

The custom rules catch stuff that the global rules don't, but fortunately, we didn't have anything to fix here.

I also length matched the D- and D+ lines by making D- and D+ both use vias to cross each other; I also adjusted the spacking and width of the tracks of the main run based on this calculation from eeweb:

With this, I think we're finally finished with this revision 🥳

Hello, I like this project and would like to reproduce it with qmtech spartan 6 board. Can I use USB3300 for USB interface or is there some special feature of 3320 being used?

If so, don't you happen to have one extra unpopulated PCB to sell?

Thank you.

I ran into some issues when ordering the PCB from JLCPCB, so I had to make some minor adjustments:

1. Changed the footprint for the toslink ports to the T8 variation vs. the T10. I can't find the PLR135/T10 part anywhere, and JLCPCB only had the T8. The only difference is the addition of two NPTH for the plastic mounting feet, so either the T10 or T8 variations can be used.

2. Fix the USB-C port rotation for the POS file; it is flipped 180 degrees in the JLCPCB render

3. Move power traces away from board edge The JLCPCB capabilities section says that traces must be >=.2mm from the edge:

So I just moved the power traces about .1mm; the only thing that it might cause issue with is that they're closer to the shield PTHs, but they still have about .4mm clearance to copper.

4. Adjusted the board width for TOSLINK port clearance so that it can be flush with the case.

BTW, you may want to update your JLCPCB plugin, I note that the part assignments file was in a different format.

I realize that S/PDIF is a different protocol and may take some effort to work because of variable clock speeds, but is this something that you are thinking about implementing in the future?

Would it be possible to port this to the LUNA board?

The 8 in and out optical ports should fit comfortably on one of the two available PMOD connectors (though power draw may become an issue), and the two DACs on the other.

Applied the length matching to both the top AND bottom interfaces, fixed the main run according to these impedence calculations (because .09mm spacing was a bit too tight for comfort):

I finally found a custom ruleset that has the JLCPCB rules here: https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e

I added that to the custom rules on the project and I adjusted the values to match. This should be all of their minimums. I also removed some bogus rules (like trace to vcut, since we aren't panelizing this, and maximum PTH size, which produced incorrect results).

There are about 149 errors left now, but about 1/4 of them are just some ground vias having too small an annular ring (0.1250 vs. 0.13), and a good chunk of them are just here:

The convolver can be enabled with the USE_CONVOLUTION flag. Once the design has been synthesized with USE_CONVOLUTION enabled you can enable the convolver by either pressing the first platform button or via the TOGGLE_CONVOLUTION (1) vendor usb control request.

The concolver uses the amlib.dsp.convolution.mac convolver for now. In the future an option to use FFT convolution may be added.